The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Differential jitter between a clock signal and a data signal can lead to performance degradation in data interfaces both within an integrated circuit and between integrated circuits. In System-on-Chips (SoCs) that include a power delivery network (PDN), local switching currents may lead to local variations in the supply voltage received by circuit blocks of the SoC. The supply variation will lead to jitter being introduced as a result of modulation in the delay across the circuit block.